Ultra-low power subthreshold current- mode logic utilising PMOS load device

Introduction: Current-mode logic (CML) circuits are widely used in many high-speed and high-performance applications [1]. The differential topology of CML circuits provides high immunity to supply noise and crosstalk, while reduced voltage swing at the output helps to operate the circuit in very high frequencies with low noise generation [1, 2]. These properties make the MOS CML (MCML) topology an attractive candidate for ultra-low power applications as well. This, however, usually requires that the circuit be biased in the subthreshold region, conducting a very low tail current and still producing a sufficiently large output swing. While several techniques for implementing CMOS logic circuits with transistors in the subthreshold regime and with very low power dissipation have been already introduced [3], the design of ultra-low power MCML circuits is yet an open research subject. This Letter introduces a new approach for implementing MCML circuits that can be applied to digital CMOS technologies.